// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_int_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_INT_REG_REG_OFFSET_H__
#define __HIPCIEC_AP_INT_REG_REG_OFFSET_H__

/* HIPCIEC_AP_INT_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE                       (0x10000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_AP_INT_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_VECTOR_NUM_REG       (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x0)   /* MSIX Vector Number */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_COAL_CTRL_REG        (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x4)   /* MSIX Vector Coal Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_COAL_EVENT_REG       (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x8)   /* MSIX Coal Event Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_COAL_TIME_UNIT_REG   (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0xC)   /* MSIX Coal Time Unit */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_MSG_ADDR_REG         (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x10)  /* MSIX Message Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_MSG_UP_ADDR_REG      (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x14)  /* MSIX Message up Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_MSG_DATA_REG         (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x18)  /* MSIX Message Data */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_VECTOR_CTRL_REG      (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x1C)  /* MSIX Vector Control */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_PENDING_BIT_REG      (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x20)  /* MSIX Pending Bits */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_MSIX_SRAM_INIT_STATUS_REG (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x24)  /* MSIX sram initial status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_HOST_ACCESS_STATUS_REG    (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x50)  /* Host access tlp status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_TLP_CNT_CFG_REG           (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x54)  /* Tlp count configure */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_HOST_TLP_CNT_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x58)  /* Host TLP Count0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_HOST_TLP_CNT_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x5C)  /* Host TLP Count1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_DMA_INPUT_STATUS_REG      (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x60)  /* dma input status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_DMA_OUTPUT_STATUS_REG     (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x64)  /* dma output status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_NVME_INPUT_STATUS_REG     (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x68)  /* nvme input status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_NVME_OUTPUT_STATUS_REG    (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x6C)  /* nvme output status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_FSM_STATUS_REG            (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x70)  /* fsm status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_LINK_DOWN_IDLE_STATUS_REG (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x74)  /* Link down idle status */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_ECC_ERR_INT_SRC_STS_REG   (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x78)  /* ECC error int src */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_ECC_ERR_MASK_REG          (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x7C)  /* ECC Error Mask */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_ECC_ERR_INT_STS_REG       (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x80)  /* ECC error int sts */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_ECC_ERR_INJECT_REG        (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x84)  /* ECC Error inject */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_NET_ECAM_BUS_NUM_REG      (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x100) /* Network ECAM Bus number */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_NET_PF_NUM_REG            (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x104) /* Network PF Number */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_NET_FIRST_VF_NUM_REG      (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x108) /* Network VF First  Number */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_NET_VF_STRIDE_REG         (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x10C) /* Network VF Stride */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_NET_ECAM_BASE_REG         (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x110) /* Network ECAM BASE */
#define HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_ERR_RESPONSE_REG          (HiPCIECTRL40V200_HIPCIEC_AP_INT_REG_BASE + 0x114) /* Sync error response */

#endif // __HIPCIEC_AP_INT_REG_REG_OFFSET_H__
